The present invention relates to an information processing apparatus such as personal computer (PC) and its display controller and more particularly, to rotation display of display data in the information processing apparatus.
A method for rotation display of display data has hitherto been known as described in, for example, JPA-6-289848 in which one address generation method is switched to another.
In the above prior art, a display address generator 16051 for controlling the address of a VRAM 1606 is provided in a display controller 1605 as shown in FIG. 16 and when a rotation display is instructed by a CPU 1601, the display address generator 16051 switches one display address generation method to another so that the VRAM 1606 may be accessed through an address bus 16053. Besides, by causing a display control unit 16052 to convert the bit sequence of the display data, the contents of the VRAM 1606 can be 180xc2x0 rotated and displayed. In this manner, the prior art realizes rotation display at a higher speed than that in a scheme in which rewrite operation is effected through software.
With the prior art method for rotation display, 180xc2x0 rotation can be implemented easily without sacrificing the display performance but 90xc2x0 rotation display and 270xc2x0 rotation display can be implemented only at the cost of the display performance.
Typically, a DRAM is used as VRAM 1606 and with the aim of improving the speed of data transfer to the display controller, the VRAM 1606 is accessed through a burst access to the DRAM. The burst access is a memory access method for sequential write and read of data. The burst access is permissible only for addresses on the same row of the DRAM. In the 180xc2x0 rotation display, the sequence of display data access is in the row address direction like the normal display and therefore the burst access to the DRAM can be utilized without affecting the display performance. But in the case of the 90xc2x0 and 270xc2x0 rotation displays, the sequence of display data access is in the column address direction and the burst access to the DRAM cannot be utilized. Accordingly, in this case, display data is read out by a single access to the DRAM and the speed of data transfer to the display controller is decreased to degrade the display performance.
Therefore, an object of the present invention is to provide a display controller or an information processing apparatus which can execute 90xc2x0, 180xc2x0 and 270xc2x0 rotation displays without sacrificing the display performance.
To accomplish the above object, according to the present invention, an information processing apparatus comprises:
a processing unit;
a memory unit for storing display data processed by the processing unit;
a display image rotation engine which is coupled with a buffer memory to sequentially transfer display data to the buffer memory and which responds to a command of predetermined timing for display data update to store the display data, stored in the buffer memory, in the memory unit in read sequence different from write sequence;
a display controller for delivering the display data stored in the memory unit by means of the rotation engine to a display device; and
a bus for mutually coupling the processing unit, the memory unit, the display controller and the rotation engine.
In an embodiment of the present invention, the display image rotation engine is coupled to a buffer memory having n*n+n areas each being adapted to store display data pieces corresponding to m/n*L/n pixels, where L is a predetermined number of pixels in the display data on the same row, m is the number of rows and n is a numeral for equally dividing each of the L and m, and while sequentially writing display data pieces for m rows in a unit of L pixels to the n*n areas, reads display data pieces for m pixels on the same column, column by column, from the remaining n areas and writes sequentially display data pieces to the n areas for which read operation has ended.
In another embodiment of the invention, the display image rotation engine is coupled with a buffer memory having a plurality of areas each storing display data pieces corresponding in number to (a predetermined number L of pixels of the display data on the same row)*(the number m of rows) and while writing display data pieces for m rows in a unit of L pixels to one area, reads display data pieces for m pixels on the same column, column by column, from the other area.